Signal Chain¶
Waveform Generation Path
Overview¶
REVA v4.0 employs a layered signal chain architecture.
Each stage performs a dedicated function and passes its output to the following stage.
This separation improves repeatability and preserves deterministic timing.
Signal Chain¶
Carrier Frequency
↓
Timer1 Carrier Engine
↓
Packet Executor
↓
Timer2 Packet Scheduler
↓
OC1A / OC1B
↓
IR2304
↓
Half Bridge
↓
Load
Signal Processing Stages¶
| Stage | Purpose |
|---|---|
| Timer1 | Carrier generation |
| Timer2 | Packet scheduling |
| Output Channels | Logic-level waveform |
| IR2304 | Gate drive |
| Half Bridge | Power conversion |
| Load | External experiment |
Design Philosophy¶
Each stage performs a single responsibility.
Timing remains isolated from operator interaction.