Timer1 Carrier Engine¶
Generation of the Fundamental Carrier Waveform
Overview¶
Timer1 forms the carrier engine of REVA v4.0.
Its purpose is to generate the continuous pulse train from which all packetized waveforms are constructed.
The carrier engine operates independently from:
- packet scheduling,
- display updates,
- button handling,
- menu navigation,
- EEPROM activity.
This separation allows the carrier frequency to remain stable regardless of operator interaction.
Position Within REVA¶
Packet Library
↓
Packet Executor
↓
Timer2 Scheduler
↓
Timer1 Carrier Engine
↓
OC1A / OC1B
↓
D9 / D10
↓
IR2304
↓
Half Bridge
Timer1 represents the lowest timing layer within the waveform generation chain.
All packet structures ultimately depend upon the carrier generated by Timer1.
Why Timer1?¶
The ATmega328P contains multiple hardware timers.
Timer1 was selected because:
- it is a 16-bit timer,
- it provides high frequency resolution,
- it supports hardware waveform generation,
- it provides direct access to OC1A and OC1B.
These characteristics make Timer1 the most suitable timer for carrier synthesis.
Carrier Philosophy¶
REVA separates:
Carrier Frequency
from
Packet Geometry
The carrier determines the pulse repetition rate.
The packet system determines when the carrier is allowed to appear.
This separation allows a single carrier frequency to be combined with many different packet structures.
Carrier Frequency¶
The carrier frequency is selected within the firmware.
Example:
#define CARRIER_HZ 90000
Typical operating frequencies include:
| Frequency | Application |
|---|---|
| 10 kHz | Low-frequency experiments |
| 50 kHz | General operation |
| 90 kHz | Harmonic packet operation |
| 120 kHz | High-frequency operation |
| 250 kHz | Extended operating range |
The carrier remains fixed during operation.
Packet structures modify the envelope rather than the carrier itself.
Hardware Outputs¶
Timer1 directly controls:
| Pin | Function |
|---|---|
| D9 | OC1A |
| D10 | OC1B |
These outputs drive the IR2304 half-bridge driver.
Relationship to Timer2¶
Timer1 and Timer2 perform different tasks.
Timer1¶
Responsible for:
- carrier generation,
- pulse timing,
- output waveform production.
Timer2¶
Responsible for:
- packet scheduling,
- segment timing,
- burst timing,
- packet repetition.
The two timers operate together but perform fundamentally different functions.
Timing Independence¶
The carrier engine operates independently from:
OLED Refresh
Button Scanning
Menu Navigation
EEPROM Access
Packet Selection
As a result, waveform timing remains deterministic.
Operator activity cannot directly modify carrier timing.
Engineering Perspective¶
The carrier engine can be viewed as a continuously running oscillator.
Timer2 then decides:
When the oscillator is visible
and
When the oscillator is hidden
through packet scheduling.
This layered architecture is one of the defining characteristics of REVA v4.0.