Firmware Structure¶
Internal Code Organization
Philosophy¶
REVA v4.0 separates carrier generation, packet scheduling, packet selection and operator interaction into independent subsystems.
This prevents display updates and button handling from influencing waveform timing.
Main Architecture¶
Operator
↓
OLED UI
Buttons
EEPROM
↓
Harmonic Packet Engine
↓
Packet Category
Packet Family
↓
Packet Executor
↓
Timer2 Packet Scheduler
↓
Timer1 Carrier Engine
↓
D9 (OC1A)
D10 (OC1B)
↓
IR2304 Half Bridge
Timer1¶
Timer1 generates the carrier waveform.
Outputs:
- D9 = OC1A
- D10 = OC1B
Responsibilities:
- carrier frequency
- duty ratio
- complementary output timing
Timer1 forms the fast timing domain of the instrument.
Timer2¶
Timer2 operates as the packet scheduler.
Responsibilities:
- packet timing
- segment transitions
- ON intervals
- OFF intervals
- packet execution timing
Timer2 forms the medium timing domain.
Harmonic Packet Engine¶
The Harmonic Packet Engine organizes waveform structures using:
- packet category
- packet family
- pulse scale
- gap scale
The operator selects the structure.
The firmware executes the timing.
User Interface¶
The OLED and buttons are separated from waveform generation.
Operator interaction occurs outside the critical timing path.
EEPROM¶
EEPROM stores persistent configuration values.
Typical stored values include:
- carrier frequency
- carrier duty
- active category
- start family
- pulse scale
- gap scale
Stability¶
The firmware structure preserves the fixed REVA v4.0 hardware architecture.
No additional pins, timers or external timing hardware are assumed.