Signal Chain¶
From Mathematical Definition to Half-Bridge Output
Overview¶
The signal chain describes how a waveform travels through REVA v4.0.
Rather than generating pulses directly from user input, REVA processes waveform information through a series of independent layers.
Each layer performs a specific task and passes information to the next stage.
This architecture improves:
- determinism,
- reproducibility,
- maintainability,
- timing integrity.
Complete Signal Path¶
Operator
↓
Packet Category
↓
Packet Family
↓
Packet Executor
↓
Timer2 Scheduler
↓
Timer1 Carrier Engine
↓
OC1A / OC1B
↓
D9 / D10
↓
IR2304
↓
Half Bridge Output
Information Flow¶
A useful way to understand REVA is to examine what information is flowing between each stage.
Operator
↓ configuration
Packet Category
↓ mathematical relationship
Packet Family
↓ waveform geometry
Packet Executor
↓ timing instructions
Timer2
↓ scheduling events
Timer1
↓ carrier pulses
IR2304
↓ power switching
Half Bridge
Each layer transforms information into a more concrete representation.
Operator Layer¶
The operator defines the experiment.
Typical selections include:
- carrier frequency,
- packet category,
- packet family,
- pulse scaling,
- gap scaling.
These settings define the desired waveform behavior.
The operator never directly controls output timing.
Packet Category Layer¶
A packet category defines a mathematical relationship.
Examples include:
- Harmonic
- Subharmonic
- Octave
- Fibonacci
- Lucas
- Golden Ratio
- Prime
The category determines the type of waveform structures available.
Packet Family Layer¶
Each category contains multiple packet families.
A family defines waveform geometry.
Example:
12
24
48
24
12
or
5
8
13
21
34
At this stage the waveform still exists only as numerical information.
No physical timing has yet been generated.
Packet Executor Layer¶
The Packet Executor converts waveform geometry into executable timing data.
Responsibilities include:
- family interpretation,
- segment processing,
- pulse scaling,
- gap scaling.
The executor acts as a translator between mathematics and timing.
Timer2 Scheduler Layer¶
Timer2 controls packet timing.
It determines:
- segment duration,
- segment transitions,
- gap intervals,
- packet repetition.
Timer2 therefore creates the packet envelope.
Timer1 Carrier Layer¶
Timer1 generates the carrier waveform.
Responsibilities include:
- pulse generation,
- carrier frequency,
- complementary outputs.
Timer1 remains independent from packet geometry.
Output Stage¶
Timer1 directly drives:
| Pin | Function |
|---|---|
| D9 | OC1A |
| D10 | OC1B |
These outputs connect to the IR2304 half-bridge driver.
IR2304 Driver¶
The IR2304 converts low-power logic signals into gate-drive signals suitable for MOSFET switching.
Responsibilities include:
- gate drive generation,
- level shifting,
- half-bridge control.
Half-Bridge Output¶
The half-bridge produces the final waveform delivered to the experiment.
At this point the waveform contains:
- carrier frequency,
- packet geometry,
- segment timing,
- runtime scaling.
All architectural layers have contributed to the final result.
Separation of Responsibilities¶
One of the fundamental design principles of REVA is task separation.
Operator
↓
Mathematics
↓
Execution
↓
Scheduling
↓
Carrier Generation
↓
Power Switching
Each layer performs one specific role.
This improves clarity and minimizes unwanted interactions between subsystems.
Engineering Perspective¶
The signal chain can be viewed as a progressive transformation process.
Mathematical Idea
↓
Packet Geometry
↓
Timing Geometry
↓
Carrier Modulation
↓
Power Waveform
This layered approach is one of the defining characteristics of REVA v4.0.