Firmware Layers¶
Logical Organization of REVA v4.0 Firmware
Overview¶
REVA v4.0 separates waveform generation into multiple firmware layers.
Each layer performs a specific task and passes information to the next layer.
This separation allows timing-critical waveform generation to remain independent from operator interaction, display updates and parameter management.
Layer Hierarchy¶
Operator
↓
Button Scanner
↓
User Interface
↓
Parameter Manager
↓
Packet Library
↓
Packet Executor
↓
Timer2 Scheduler
↓
Timer1 Carrier Engine
↓
D9 / D10 Outputs
Each layer has a clearly defined responsibility.
Operator Layer¶
The operator interacts with REVA through the front-panel controls.
Typical actions include:
- selecting packet families,
- adjusting pulse scaling,
- adjusting gap scaling,
- navigating menus.
Operator actions do not directly modify waveform timing.
Button Scanner¶
The button scanner monitors the physical buttons.
Responsibilities include:
- button state detection,
- press detection,
- long-press detection,
- generation of control events.
The scanner converts physical button activity into firmware commands.
User Interface Layer¶
The user interface presents information on the OLED display.
Responsibilities include:
- menu navigation,
- parameter visualization,
- operator feedback,
- status display.
The user interface does not generate waveforms.
Parameter Manager¶
The Parameter Manager maintains all runtime settings.
Examples include:
- selected packet family,
- pulse scale,
- gap scale,
- stored configuration values.
This layer acts as the bridge between user interaction and waveform generation.
Packet Library¶
The Packet Library stores mathematical packet definitions.
Examples include:
- Harmonic,
- Subharmonic,
- Octave,
- Fibonacci,
- Lucas,
- Golden Ratio,
- Prime.
The library contains waveform geometry but performs no timing calculations.
Packet Executor¶
The Packet Executor converts packet definitions into executable timing information.
Responsibilities include:
- family interpretation,
- segment processing,
- pulse scaling,
- gap scaling.
This layer transforms mathematical structures into scheduler instructions.
Timer2 Scheduler¶
Timer2 controls packet timing.
Responsibilities include:
- segment timing,
- gap timing,
- packet repetition,
- envelope generation.
Timer2 determines when carrier bursts appear.
Timer1 Carrier Engine¶
Timer1 generates the carrier waveform.
Responsibilities include:
- carrier frequency generation,
- duty-cycle generation,
- complementary outputs.
Timer1 operates independently from packet geometry.
Output Layer¶
Timer1 directly drives:
| Pin | Function |
|---|---|
| D9 | OC1A |
| D10 | OC1B |
These outputs are connected to the IR2304 half-bridge driver.
Separation of Responsibilities¶
One of the fundamental design principles of REVA is that each layer performs one task.
User Interaction
↓
Parameter Management
↓
Packet Geometry
↓
Packet Timing
↓
Carrier Generation
↓
Output Signals
This architecture improves reproducibility and simplifies firmware maintenance.