Firmware Structure¶

Philosophy¶

REVA separates carrier generation, packet scheduling and operator interaction into independent subsystems.

This prevents display updates and button handling from influencing waveform timing.

Main Architecture¶

Operator
    ↓

OLED UI
Buttons
EEPROM

    ↓

Packet Family Engine

    ↓

Packet Table Builder

    ↓

Timer2 Event Scheduler

    ↓

Envelope ON/OFF

    ↓

Timer1 Carrier Generator

    ↓

D9 (OC1A)
D10 (OC1B)

    ↓

IR2304 Half Bridge

Timer1¶

Timer1 generates the protected complementary carrier.

Outputs:

D9 = OC1A
D10 = OC1B

Responsibilities:

carrier frequency
duty ratio
complementary outputs

Timer1 does not execute an interrupt for every carrier cycle.

Timer2¶

Timer2 operates as an event scheduler.

Responsibilities:

packet timing
burst transitions
packet execution

The ISR only wakes at packet ON/OFF boundaries.

Packet Table Executor¶

Packet families are converted into tables consisting of ON and OFF durations.

The executor walks through the table and enables or disables the carrier.

This architecture minimizes processor load and provides deterministic timing.

User Interface¶

The OLED and buttons are completely separated from the pulse engine.

Changing parameters does not disturb carrier generation.

EEPROM¶

EEPROM stores:

frequency
duty cycle
packet family
packet settings

Values survive power cycles.

Source Files¶

Main Firmware¶

REVA_v3.3beta20d_IR2304_locked_show_ui.ino

Contains:

Timer configuration
ISR handlers
OLED display
EEPROM
packet family logic

Packet Structures¶

REVA_PacketTable.h

Defines:

PacketStep
SegmentDef
PacketTable

These structures describe the packet executor.

Derived Metrics¶

REVA_DerivedMetrics.h

Defines:

struct DerivedMetrics
{
    float mainDutyPercent;
    float mainPeriodUs;
    float mainOnUs;

    uint16_t periodCycles;
    uint16_t onCycles;
    uint16_t offCycles;

    bool limited;
};

These values are calculated from operator settings and are used for display and packet calculations.