Hardware¶
Physical Architecture
Overview¶
REVA v4.0 is implemented on a fixed hardware platform.
The hardware is intentionally stable and forms the foundation upon which all firmware layers operate.
No additional timing hardware is required.
All waveform generation is performed internally by the ATmega328P using Timer1 and Timer2.
Hardware Composition¶
Arduino Nano
↓
ATmega328P
↓
Timer1 Carrier Engine
Timer2 Packet Scheduler
↓
D9 / OC1A
D10 / OC1B
↓
IR2304
↓
Half Bridge
Major Components¶
| Component | Function |
|---|---|
| Arduino Nano | Main platform |
| ATmega328P | Central controller |
| Timer1 | Carrier generation |
| Timer2 | Packet scheduling |
| D9 (OC1A) | Half-bridge output A |
| D10 (OC1B) | Half-bridge output B |
| IR2304 | Gate driver |
| Half Bridge | Power stage |
| OLED | Operator display |
| Four Buttons | User interface |
| EEPROM | Parameter storage |
Hardware Architecture¶
The hardware of REVA is divided into several layers.
Controller Layer
↓
Timing Layer
↓
Output Layer
↓
Driver Layer
↓
Power Layer
Each layer performs a dedicated function.
The separation between these layers allows firmware development to evolve without requiring modifications to the physical platform.
Design Philosophy¶
The hardware architecture is intentionally frozen.
Firmware evolution occurs without requiring modifications to the electrical platform.
This separation improves repeatability and long-term compatibility.
Hardware Chapters¶
Controller¶
The ATmega328P forms the computational core of REVA.
Output Channels¶
Timer1 produces two hardware-generated outputs.
Driver Stage¶
The gate driver translates digital timing information into switching signals.
Power Stage¶
The half bridge delivers the waveform to the external load.
User Interface¶
Operator interaction occurs through the display and four buttons.
Resource Allocation¶
Microcontroller resources are assigned deterministically.