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REVA v3.3beta20d
REVA v3.3beta20d
- Overview
- Quick Tour
- Instrument Identity
  Instrument Identity
- Internal Subsystems
- Document Map
- Architecture
  Architecture
  - Overview
  - Timer1
  - Timer2
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  - Packet Executor
  - EEPROM
  - OLED
- Hardware
  Hardware
  - Overview
  - ATmega328P
  - D9 OC1A
  - D10 OC1B
  - IR2304
  - Half Bridge
  - OLED Display
  - Buttons
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- Firmware
  Firmware
  - Overview
  - Setup
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  - Interrupts
  - Timer1 ISR
  - Timer2 ISR
  - Timing Domains
  - EEPROM Storage
- Source Code
  Source Code
- Operator
  Operator
  - Overview
  - Startup
  - Controls
  - Display
  - Profiles
  - Workflow
  - Measurements
- Parameters
  Parameters
- Packet Families
  Packet Families
  - Overview
  - Equal
  - Increasing
  - Decreasing
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  - Sparse
  - Exponential
  - Fibonacci
  - Lucas
  - Golden Ratio
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  - Ping
  - Random
- Signal Chain
  Signal Chain
- State Machine
  State Machine
- Protection
  Protection
- Waveforms
  Waveforms
  - Overview
  - Packet Gallery
- Theory
  Theory
  - Overview
  - Frequency
  - Duty Cycle
  - Carrier
  - Burst
  - Packet
  - Segment Segment
    Table of contents
    
    Definition
    
    Structure
    
    Controlled By
    
    Related Pages
  - Envelope
  - Timing
  - Packet Geometry
  - Packet Density
  - Packet Spacing
REVA v4.0
REVA v4.0
- Overview
- Quick Tour
- Instrument Identity
- Development Philosophy
- Architecture
  Architecture
  - Overview
  - Core Architecture
    Core Architecture
    
    Signal Chain
    
    Timer1 Carrier Engine
    
    Timer2 Packet Scheduler
    
    Packet Executor
    
    Harmonic Packet Library
  - Internal Design
    Internal Design
    
    Firmware Layers
    
    State Machine
    
    Startup Sequence
    
    EEPROM Storage
  - Timing System
    Timing System
    
    Timing Hierarchy
    
    Timing Mathematics
  - Data Flow
    Data Flow
    
    Data Flow
    
    Output Generation
    
    Design Principles
- Operator Guide
  Operator Guide
- Parameters
  Parameters
- Packet Categories
  Packet Categories
  - Overview
  - Harmonic
  - Subharmonic
  - Octave
  - Odd / Even
  - Prime
  - Fibonacci
  - Lucas
  - Golden Ratio
- Theory
  Theory
- Examples
  Examples
- Waveforms
  Waveforms
- Hardware
  Hardware
  - Overview
  - ATmega328P
  - D9 / OC1A
  - D10 / OC1B
  - IR2304
  - Half Bridge
  - Buttons
  - OLED Display
  - Resource Map
- Firmware
  Firmware
  - Overview
  - Setup
  - Loop
  - Interrupts
  - Timer1 ISR
  - Timer2 ISR
  - Timing Domains
  - Startup Sequence
- Source Code
  Source Code
- Signal Chain
  Signal Chain
- Display
  Display
- Advanced
  Advanced
- Reference
  Reference

Table of contents

Definition
Structure
Controlled By
Related Pages

Segment¶

Definition¶

A segment consists of:

Burst
+
Gap

Structure¶

ON
OFF

Controlled By¶

REVA_v3.3beta20d/parameters/pulse_scale
REVA_v3.3beta20d/parameters/gap_scale

Related Pages¶

packet

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