Architecture¶
Internal Structure of REVA v4.0
Overview¶
REVA v4.0 separates waveform generation into multiple independent subsystems.
This layered architecture allows packet generation, user interaction, parameter management and display functions to operate without interfering with timing-critical waveform generation.
The architecture is built around two hardware timers:
- Timer1
- Timer2
which together form the foundation of the Harmonic Packet Engine.
Architecture at a Glance¶
Operator Interaction
↓
Firmware Layers
↓
Data Flow
↓
Packet System
↓
Timing System
↓
Output Generation
The pages within this chapter describe each of these layers in detail.
Fundamental Design Philosophy¶
REVA is built around several core principles:
- deterministic timing,
- separation of responsibilities,
- carrier independence,
- mathematical packet organization,
- reproducible waveform generation.
These principles influence every subsystem within the instrument.
For a detailed discussion see:
Firmware Architecture¶
The firmware is organized into multiple logical layers.
Operator
↓
Button Scanner
↓
User Interface
↓
Parameter Manager
↓
Packet Library
↓
Packet Executor
↓
Timer2 Scheduler
↓
Timer1 Carrier Engine
↓
D9 / D10
Relevant pages:
Startup and Runtime Operation¶
Before waveform generation begins, REVA performs a defined initialization sequence.
During operation the firmware moves through several logical states while maintaining continuous packet execution.
Relevant pages:
Timing Architecture¶
REVA operates using multiple nested timing layers.
Carrier Cycle
↓
Burst
↓
Segment
↓
Packet
↓
Packet Family
↓
Continuous Output Stream
Relevant pages:
Packet System¶
Packet generation is based on mathematical packet libraries.
The packet system transforms abstract mathematical structures into executable timing information.
Relevant pages:
Hardware Timers¶
REVA separates carrier generation from packet scheduling.
Timer1¶
Responsible for:
- carrier generation,
- pulse timing,
- output waveform production.
Timer2¶
Responsible for:
- packet scheduling,
- segment timing,
- burst timing,
- packet repetition.
Relevant pages:
Output Generation¶
The final waveform is produced through cooperation between:
- packet geometry,
- timing control,
- carrier generation,
- output hardware.
Relevant pages:
Architecture Navigation¶
Foundations¶
Firmware¶
Packet Engine¶
Timing¶
Hardware¶
Design Goals¶
The architecture of REVA v4.0 aims to provide:
- deterministic timing,
- hardware simplicity,
- reproducible operation,
- independent subsystems,
- mathematical packet organization,
- predictable waveform generation.