Timer1 ISR¶
Carrier Timing Layer
Overview¶
Timer1 forms the fast timing layer of REVA.
Its role is to generate the carrier waveform used by all packet structures.
The carrier is the foundation upon which packet timing is built.
Position Within REVA¶
Packet Executor
↓
Timer2 Scheduler
↓
Timer1 Carrier Engine
↓
OC1A / OC1B
↓
D9 / D10
Responsibilities¶
Timer1 is responsible for:
- carrier frequency generation,
- pulse timing,
- complementary output generation,
- hardware-level waveform production.
Output Pins¶
| Output | Arduino Pin | ATmega328P Function |
|---|---|---|
| OC1A | D9 | Timer1 output A |
| OC1B | D10 | Timer1 output B |
These pins drive the IR2304 input stage.
Timing Domain¶
Timer1 belongs to the fast timing domain.
Fast Domain
Timer1
OC1A
OC1B
D9
D10
This domain must remain isolated from slow tasks such as display updates.
Relationship to Timer2¶
Timer1 produces the carrier.
Timer2 determines when the carrier appears inside the packet envelope.
Timer1 = carrier
Timer2 = envelope
The final waveform is created by the interaction of both timers.
Design Philosophy¶
Timer1 should be treated as the carrier oscillator of REVA.
Higher firmware layers may configure or enable its behavior, but they should not create carrier timing in software.