Timing Domains¶
Separation of Responsibilities
Overview¶
REVA separates firmware activity into timing domains.
This prevents slow software tasks from disturbing waveform generation.
Timing Hierarchy¶
Slow Domain
Buttons
Menus
Display
EEPROM
↓
Medium Domain
Packet Executor
Timer2 Scheduler
↓
Fast Domain
Timer1 Carrier Engine
OC1A / OC1B
D9 / D10
Slow Domain¶
The slow domain contains user-facing and background tasks.
Responsible for:
- button scanning,
- menu handling,
- display updates,
- parameter editing,
- EEPROM activity.
This domain may vary in execution time.
It must not define waveform timing.
Medium Domain¶
The medium domain contains packet execution and scheduling.
Responsible for:
- packet family execution,
- segment progression,
- gap timing,
- packet envelope timing.
This domain shapes the carrier into packets.
Fast Domain¶
The fast domain contains carrier generation.
Responsible for:
- carrier timing,
- pulse generation,
- complementary outputs,
- direct output pin activity.
This domain is the most timing-critical part of REVA.
Domain Separation¶
Each domain has a different purpose.
| Domain | Purpose | Timing Critical |
|---|---|---|
| Slow | User interface and storage | Low |
| Medium | Packet scheduling | Medium |
| Fast | Carrier generation | High |
Design Rule¶
Slow-domain activity must not disturb medium-domain or fast-domain timing.
Display update
≠
Carrier timing
Button scan
≠
Packet timing
This rule is central to REVA v4.0.
Engineering Perspective¶
The final waveform is stable because timing-sensitive work is moved away from the main loop and into the timer system.
The user interface remains responsive, but the waveform remains deterministic.