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REVA Documentation
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REVA Documentation
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Quick Tour
Instrument Identity
Development Philosophy
Internal Subsystems
Document Map
Architecture
Architecture
Overview
Timer1
Timer2
Packet Scheduler
Packet Executor
EEPROM
OLED
Hardware
Hardware
Overview
ATmega328P
D9 OC1A
D10 OC1B
IR2304
Half Bridge
OLED Display
Buttons
Resource Map
Firmware
Firmware
Overview
Setup
Loop
Interrupts
Timer1 ISR
Timer2 ISR
Timing Domains
EEPROM Storage
Source Code
Source Code
Overview
Firmware Structure
Complete Source Code
Downloads
Operator
Operator
Overview
Startup
Controls
Display
Profiles
Workflow
Measurements
Parameters
Parameters
Overview
Carrier Frequency
Carrier Duty
Packet Burst Count
Packet Family
Pulse Scale
Gap Scale
Final Gap
Custom Segments
Parameter Interactions
Packet Families
Packet Families
Overview
Equal
Increasing
Decreasing
Decreasing
Table of contents
Character
Pattern
Similar Families
Dense
Sparse
Exponential
Fibonacci
Lucas
Golden Ratio
Prime
Mirror
Symmetric
Ping
Random
Signal Chain
Signal Chain
Overview
Complete Signal Path
Operator to Packet
Packet Scheduler to Executor
Executor to Timer2
Timer2 to Timer1
Timer1 to Half Bridge
State Machine
State Machine
Overview
Idle State
Burst State
Gap State
Repeat State
Packet Complete State
State Transition Table
Packet Scheduler Protection
Protection
Protection
Overview
Modification Strategy
Timer1 Protection
Timer2 Protection
Packet Executor Protection
OLED Protection
EEPROM Protection
Theory
Theory
Overview
Frequency
Duty Cycle
Carrier
Burst
Packet
Segment
Envelope
Timing
Packet Geometry
Packet Density
Packet Spacing
Table of contents
Character
Pattern
Similar Families
Decay Family
¶
Character
¶
Progressive contraction.
Pattern
¶
32 16 8 4 2 1
Similar Families
¶
exp