REVA v3.3beta20d¶

Packetized Pulse Synthesizer

REVA Front Panel

Overview¶

REVA v3.3beta20d is a laboratory pulse synthesizer designed to generate packetized carrier bursts with deterministic timing.

The instrument separates:

carrier generation,
packet scheduling,
operator interaction,
display functions,

into independent subsystems.

This architecture allows waveform generation to remain stable while parameters and packet families are adjusted.

Main Characteristics¶

Feature	Description
Controller	ATmega328P
Carrier Engine	Timer1
Packet Engine	Timer2
Outputs	D9 / OC1A and D10 / OC1B
Driver	IR2304
Display	OLED
Storage	EEPROM
Interface	Four buttons

Architecture at a Glance¶

Operator
    ↓
Packet Scheduler
    ↓
Packet Executor
    ↓
Timer2
    ↓
Timer1
    ↓
D9 / D10
    ↓
IR2304
    ↓
Half Bridge

Internal Layers¶

Display Layer
        ↑
Operator Layer
        ↑
Packet Layer
        ↑
Carrier Layer

Fast timing functions remain isolated from slower supervisory functions.

This separation is one of the fundamental design principles of REVA.

Handbook Structure¶

Configuration¶

Internal Operation¶

Hardware¶

hardware

Firmware¶

Protected Areas¶

protection

Operator Information¶

operator

Quick Tour¶

New readers may find the following order useful.

1. Configuration¶

Additional information:

quick_tour

Instrument Identity¶

REVA v3.3beta20d is organized around independent subsystems.

Further information:

Internal Subsystems¶

Subsystem	Description
parameters	Operator configuration
packet_families	Packet geometry
signal_chain	Information flow
state_machine	Internal execution
architecture	Resource organization
hardware	Physical resources
firmware	Software organization
protection	Protected areas
operator	User interface

Additional information:

internal_subsystem

Document Map¶

REVA
│
├── Parameters
├── Packet Families
├── Signal Chain
├── State Machine
├── Architecture
├── Hardware
├── Firmware
├── Protection
└── Operator

Further information:

document_map

Typical Waveforms¶

Half-Bridge Output¶

Half Bridge Output

Complementary carrier bursts generated by Timer1 and delivered to the half bridge.

Packet Structure¶

Packet Structure

Packet repetition controlled by Timer2 and the packet engine.

Segment Geometry¶

Segment Geometry

Fine structure inside individual bursts.

Signal Flow¶

Operator
    ↓
Parameters
    ↓
Packet Scheduler
    ↓
Packet Executor
    ↓
Timer2
    ↓
Timer1
    ↓
D9 / D10
    ↓
Half Bridge

Architecture¶

            Operator
                │
                ▼
        Packet Scheduler
                │
                ▼
        Packet Executor
                │
                ▼
             Timer2
                │
                ▼
             Timer1
                │
                ▼
            D9 / D10
                │
                ▼
            IR2304
                │
                ▼
           Half Bridge

Design Philosophy¶

REVA is organized as a collection of cooperating subsystems.

Every subsystem has a clearly defined responsibility.

Fast timing functions remain isolated from slower user-interface functions.

Resources have single ownership and communicate through well-defined interfaces.

This separation allows REVA to operate as a deterministic laboratory pulse synthesizer.

The architecture is designed to preserve timing stability while allowing packet families and operating parameters to be modified safely.