Firmware¶

Internal Software Architecture of REVA v4.0

Overview¶

REVA v4.0 uses a layered firmware architecture designed to preserve deterministic waveform timing.

User interaction, display activity and parameter handling are separated from waveform generation.

This separation allows the instrument to remain responsive while the generated waveform remains stable.

Firmware Structure¶

Power Applied
        ↓
setup()
        ↓
Startup Sequence
        ↓
loop()
        ↓
User Interface
        ↓
Packet Executor
        ↓
Timer2 Scheduler
        ↓
Timer1 Carrier Engine
        ↓
D9 / D10

Functional Layers¶

Layer	Purpose
`setup()`	Initializes the instrument
Startup Sequence	Establishes a known operating state
`loop()`	Handles non-critical background tasks
User Interface	Converts button actions into parameter changes
Packet Executor	Converts packet families into timing instructions
Timer2 Scheduler	Controls packet envelope timing
Timer1 Carrier Engine	Generates the carrier waveform
Outputs	Drive D9 / D10 for the IR2304 stage

Timing Domains¶

REVA separates firmware activity into timing domains.

Slow Domain

Buttons
Menus
Display
EEPROM

↓

Medium Domain

Packet Executor
Timer2 Scheduler

↓

Fast Domain

Timer1 Carrier Engine
OC1A / OC1B
D9 / D10

This hierarchy prevents slow firmware tasks from disturbing timing-critical waveform generation.

Core Principle¶

The main firmware principle is:

Operator activity must not disturb waveform timing.

The operator may change parameters, select families or view the display.

The actual pulse timing remains controlled by the timer subsystem.

Firmware Chapters¶

Initialization¶

Background Processing¶

loop

Interrupt System¶

Timing Architecture¶

timing_domains