Design Constraints¶

Architectural Boundaries

Overview¶

REVA v4.0 was developed under a set of fixed assumptions.

These assumptions define the architecture of the instrument and preserve compatibility between firmware revisions.

Fixed Hardware¶

Arduino Nano
ATmega328P
Timer1 Carrier Engine
Timer2 Packet Scheduler
D9 / OC1A
D10 / OC1B
IR2304
Half Bridge
OLED
Four Buttons
EEPROM

Timing Principle¶

Timer2
        ↓
Packet Scheduling

Timer1
        ↓
Carrier Generation

Timing-critical functions remain isolated.

Resource Allocation¶

Timer1
    Carrier Engine

Timer2
    Packet Scheduler

D9
    OC1A

D10
    OC1B

Forbidden Assumptions¶

REVA v4.0 does not assume:

External timing hardware
Additional microcontrollers
FPGA devices
DMA controllers
External libraries
Additional output pins
Alternative timer resources

Design Philosophy¶

The architecture favors:

deterministic timing,
repeatability,
simplicity,
long-term compatibility,
separation of responsibilities.

Stability¶

These constraints form part of the identity of REVA v4.0.

Future firmware revisions should preserve these principles.