REVA v4.0¶
Harmonic Packet Engine
Overview¶
REVA v4.0 is a laboratory pulse synthesizer designed to generate deterministic packetized waveforms based upon mathematical relationships.
The instrument separates:
- carrier generation,
- packet scheduling,
- packet libraries,
- operator interaction,
- display functions,
into independent subsystems.
This architecture allows waveform generation to remain stable while packet categories and operating parameters are adjusted.
Main Characteristics¶
| Feature | Description |
|---|---|
| Controller | ATmega328P |
| Carrier Engine | Timer1 |
| Packet Engine | Timer2 |
| Outputs | D9 / OC1A and D10 / OC1B |
| Driver | IR2304 |
| Display | OLED |
| Storage | EEPROM |
| Interface | Four Buttons |
| Architecture | Harmonic Packet Engine |
Architecture at a Glance¶
Operator
↓
Packet Category
↓
Packet Library
↓
Packet Scheduler
↓
Packet Executor
↓
Timer2
↓
Timer1
↓
D9 / D10
↓
IR2304
↓
Half Bridge
Internal Layers¶
User Layer
↓
Operator Interface
↓
Display System
↓
Parameter System
↓
Packet Library
↓
Packet Scheduler
↓
Timer2 Engine
↓
Timer1 Carrier Engine
↓
Output Hardware
Packet Categories¶
REVA v4.0 organizes packet structures into mathematical categories.
Available categories include:
- Harmonic
- Subharmonic
- Octave
- Odd / Even
- Fibonacci
- Lucas
- Golden Ratio
- Prime
Each category contains multiple packet families.
Fundamental Principle¶
An experiment is defined by:
Carrier Frequency
+
Packet Category
+
Packet Family
+
Operator Adjustments
Together these determine the final waveform envelope generated by the instrument.
Documentation Structure¶
Introduction¶
Architecture¶
Operator Guide¶
Parameters¶
Packet Categories¶
Theory¶
Example Configurations¶
Waveform Gallery¶
Design Objectives¶
REVA v4.0 aims to provide:
- deterministic timing,
- reproducible experiments,
- stable hardware requirements,
- mathematically structured packet libraries,
- simple operation.
REVA v4.0 represents the first implementation of the Harmonic Packet Engine architecture.