Timing Domains¶
Overview¶
REVA separates timing responsibilities into independent domains.
This isolation improves stability and preserves waveform integrity.
Timing Domains¶
| Domain | Responsible Subsystem |
|---|---|
| Carrier Domain | Timer1 |
| Packet Domain | Timer2 |
| Operator Domain | loop() |
| Display Domain | OLED |
Hierarchy¶
Carrier Domain
↑
Packet Domain
↑
Operator Domain
↑
Display Domain
Carrier Domain¶
Responsible for:
- pulse frequency,
- duty cycle,
- complementary outputs.
Controlled by:
Timer1
Packet Domain¶
Responsible for:
- packet timing,
- burst timing,
- state transitions.
Controlled by:
Timer2
Operator Domain¶
Responsible for:
- buttons,
- parameter changes,
- EEPROM updates.
Controlled by:
loop()
Display Domain¶
Responsible for:
- operator feedback,
- screen updates.
Controlled by:
OLED subsystem