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REVA v3.3beta20d
REVA v3.3beta20d
Overview
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Instrument Identity
Instrument Identity
Overview
Origin of the Name
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Architecture
Overview
Timer1
Timer2
Packet Scheduler
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EEPROM
OLED
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ATmega328P
D9 OC1A
D10 OC1B
IR2304
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Timer2 ISR
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Equal
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Exponential
Exponential
Table of contents
Character
Pattern
Similar Families
Fibonacci
Lucas
Golden Ratio
Prime
Mirror
Symmetric
Ping
Random
Signal Chain
Signal Chain
Overview
Complete Signal Path
Operator to Packet
Packet Scheduler to Executor
Executor to Timer2
Timer2 to Timer1
Timer1 to Half Bridge
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State Machine
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Idle State
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Gap State
Repeat State
Packet Complete State
State Transition Table
Packet Scheduler Protection
Protection
Protection
Overview
Modification Strategy
Timer1 Protection
Timer2 Protection
Packet Executor Protection
OLED Protection
EEPROM Protection
Waveforms
Waveforms
Overview
Packet Gallery
Theory
Theory
Overview
Frequency
Duty Cycle
Carrier
Burst
Packet
Segment
Envelope
Timing
Packet Geometry
Packet Density
Packet Spacing
REVA v4.0
REVA v4.0
Overview
Quick Tour
Instrument Identity
Development Philosophy
Architecture
Architecture
Overview
Core Architecture
Core Architecture
Signal Chain
Timer1 Carrier Engine
Timer2 Packet Scheduler
Packet Executor
Harmonic Packet Library
Internal Design
Internal Design
Firmware Layers
State Machine
Startup Sequence
EEPROM Storage
Timing System
Timing System
Timing Hierarchy
Timing Mathematics
Data Flow
Data Flow
Data Flow
Output Generation
Design Principles
Operator Guide
Operator Guide
Overview
Controls
Workflow
Experiment Design
Parameters
Parameters
Overview
Carrier Frequency
Carrier Duty
Active Category
Start Family
Pulse Scale
Gap Scale
Packet Categories
Packet Categories
Overview
Harmonic
Subharmonic
Octave
Odd / Even
Prime
Fibonacci
Lucas
Golden Ratio
Theory
Theory
Overview
Packet Geometry
Harmonic Relationships
Subharmonics
Octaves
Mathematical Sequences
Examples
Examples
Overview
55 kHz Fibonacci
90 kHz Golden Ratio
120 kHz Harmonic
180 kHz Prime
Waveforms
Waveforms
Overview
Packet Structure
Segment Geometry
Half Bridge Output
Packet Gallery
Hardware
Hardware
Overview
ATmega328P
D9 / OC1A
D10 / OC1B
IR2304
Half Bridge
Buttons
OLED Display
Resource Map
Firmware
Firmware
Overview
Setup
Loop
Interrupts
Timer1 ISR
Timer2 ISR
Timing Domains
Startup Sequence
Source Code
Source Code
Overview
Firmware Structure
Complete Source Code
Downloads
Signal Chain
Signal Chain
Overview
Carrier Engine
Packet Scheduler
Driver Stage
Power Stage
Display
Display
Overview
Startup Screen
Status Screen
Parameter Display
Advanced
Advanced
Overview
Harmonic Packet Engine
Category Philosophy
Deterministic Timing
Experiment Reproducibility
Reference
Reference
Overview
Glossary
Abbreviations
Design Constraints
Table of contents
Character
Pattern
Similar Families
Exponential Family
¶
Character
¶
Rapid expansion.
Pattern
¶
1 2 4 8 16 32
Similar Families
¶
dec