Skip to content

Development Philosophy

The Ideas Behind REVA v4.0

Overview

REVA v4.0 represents the first implementation of the Harmonic Packet Engine architecture.

The development philosophy differs from earlier generations by emphasizing mathematical relationships and deterministic timing rather than large collections of unrelated packet patterns.

The goal is not to maximize the number of available waveforms, but to organize packet structures into coherent families.

Simplicity of Hardware

The hardware platform intentionally remains unchanged.

REVA v4.0 preserves:

  • Arduino Nano
  • ATmega328P
  • Timer1 carrier generation
  • Timer2 packet scheduling
  • D9 and D10 outputs
  • IR2304 half bridge
  • OLED display
  • Four-button interface

No additional hardware is required.

Separation of Responsibilities

REVA v4.0 separates the instrument into independent layers.

Operator
    ↓
Display System
    ↓
Parameter System
    ↓
Packet Library
    ↓
Packet Scheduler
    ↓
Timer2 Engine
    ↓
Timer1 Carrier Engine
    ↓
Output Hardware

Each subsystem performs a specific task.

This separation improves stability and reproducibility.

Mathematical Organization

Earlier generations increasingly accumulated large numbers of packet families.

Although functional, this approach became difficult to navigate.

REVA v4.0 introduces mathematical packet categories.

Examples include:

  • Harmonic
  • Subharmonic
  • Octave
  • Odd / Even
  • Fibonacci
  • Lucas
  • Golden Ratio
  • Prime

Packet families within a category share a common relationship.

This produces a more structured and predictable environment for experimentation.

Firmware-Level Configuration

REVA v4.0 assumes that the operator defines:

  • carrier frequency,
  • packet category,

inside the firmware.

The front panel is therefore reserved for runtime adjustments rather than deep configuration.

This philosophy reduces menu complexity and preserves deterministic behavior.

Deterministic Timing

Waveform timing is performed entirely by hardware timers.

Timer1
        ↓
Carrier Generation

Timer2
        ↓
Packet Scheduling

This architecture minimizes software overhead and keeps timing independent from display updates and user interaction.

Reproducibility

An experiment may be described by:

Carrier Frequency
+
Packet Category
+
Packet Family
+
Operator Adjustments

This allows experiments to be repeated and compared under identical conditions.

Stability Before Complexity

The guiding principle throughout development is:

Stability is preferred over complexity.

Additional features should never compromise:

  • timing integrity,
  • output stability,
  • reproducibility,
  • hardware simplicity.

Evolution of the REVA Family

REVA v3.3beta20d
        ↓
Packet Synthesizer

REVA v4.0
        ↓
Harmonic Packet Engine

Both generations share the same hardware foundation while adopting different approaches to packet organization.

Long-Term Vision

REVA is intended to evolve as a family of laboratory instruments.

Future generations may introduce additional mathematical libraries and packet structures while preserving the underlying principles of:

  • deterministic timing,
  • reproducibility,
  • hardware simplicity,
  • mathematical organization.

See Also